By interpreting SiC and GaN mega-trend, EDA Industries designed the SocrATE project, putting in place all the skills to develop an exclusive product, in line with the expectations of the Automotive market, such as testing coverage, quality and lowest test cost.
Specifically, the SocrATE equipment, known also as AWL-BITS MOSBTS-M180, is our breakthrough solution for Wafer Level Burn-in on WBG devices.
It is based on the experience built up in the WBG Burn-in at Package Level, extending the same approach also to Wafer Level.
The outcome is a modular and flexible prober-independent architecture, suitable for R&D, Reliability, and Manufacturing environments.
Main features
Same Test and Software Platforms for Wafer Level and Package Level Burn-in
- Extended Data-Logging and Correlation Capability
- Tracking of the Device’s whole History
- Dedicated Burn-In Data Format and STDF Output and STIF Map Management
Mixing of HTRB and HTGB stress in the same test flow
- Speed up of Burn-In time reduction process with significant impact on overall manufacturing costs
Leakage Measurement Capability
- Drift monitoring to predict device failure
- Technology learning curve optimization
Data Analysis Software Tool
- Real Time monitoring enabling Burn-In Adaptive Strategy
- Post processing analysis for feedback to R&D, Product Quality and Reliability, Manufacturing
Main features of the MOSBTS-M test platform for Wafer Level Burn-in
- Max DUT per Stage: 1800
- Drain PSU Range: [-60V to 2500V]
- Gate PSU Range: [-60V to 60V]
- Test List at Full Parallelism: HTRB/AC-HTRB/IDSS, HTGB/AC-HTGB/IGSS, IDSX, BVDSS
- Multiplexed In-Situ Measurement: Vth, RDSon, Vsd
- Monitoring: DUT Current (A) Real-Time of all 1800 DUTs in parallel
- Current Measure Range: [600nA –100uA –50mA]
- Current Measure Accuracy: [6nA – 1uA – 250uA]
- Force Current Range (parametric multiplexed test): Up to 200mA
- Failure Time Log Resolution: 1ms
High Voltage Model
- Output Voltage Range: 0 V to + 2500V
- Output Voltage Setting Accuracy: 0.05% of actual + 0.05% of rated Vout
- Output Current Range: 0 A to 1.25 A
- Maximum Output Power: 3250 W
- Ripple and noise (p-p, 20 MHz bandwidth, without load): < 250 mV
Low Voltage Model
- Output Voltage Range: -60 V to +60 V
- Output Voltage Setting Accuracy: ±0.15% of rated Vout
- Output Current Range: 0 A to 17 A
- Maximum Output Power: 1020 W
- Ripple and noise (p-p, 20 MHz bandwidth, without load): < 60 mV
Available Options
- Number of stages: Single (suggested for R&D purpose) and Multiple (from 2 up to 10 stages; typical 5 for Mass Production)
- Number of channels/stage: 900 (basic) or 1800 (basic and enhanced to support EWS tests)
- Test features: Base (including HTRB/AC-HTRB – HTGB/AC-HTGB – IDSX – BVDSS) or Base + Parametric (including Vth, RDSon, Vsd)
In addition, it is also possible to configure the Wafer Level Body Diode Stress by applying a full HW & SW different setup.
The configuration and main characteristics of the Wafer Level Test Platform for Body Diode Stress are:
- 108 channels x 12 modules, with possibility to test 1296 devices in parallel
- Up to 1296 independent FIMV channels: 2,5 A each
- Configurable to achieve up to 648 independent channels (5 A each) and 324 channels (10 A each)
- Maximum Voltage: 10V < 2mA – 7V > 2mA
Prober main features
- Common loader/unloader
- SACC Module
- Probe Card clamping mechanisms up to 520 mm
- Probe Card drawer
- Probe ID barcode reader
- Wafer inspection trays
- Cassette docking ports (FOUP) for 6” and 8”
- 6” and 8” pre-aligner system and OCR reader
- Zero footprint tester maintenance by embedded manipulator
- 6” and 8” Bernoulli handling system and universal arm
- Rooms to high temperature control (Room temperature ~ 200°C)
- 6” and 8” Wafer size chucks for 6” SiC wafer and 8” TAIKO wafer (Gold plating, Multi hole, w/o 3pin riser)
Prober operating software
- Windows 10 operating system
- Chuck tilting software algorithm embedded
- Probe mark inspection embedded
- SECSGEM automation
EDA Wafer Level Burn-in Solution approach
- Electrical Test Capabilities: HTRB and HTGB in the same flow and same HW. Parametric option available.
- Measurement: Leakage per die at full parallelism
- Test Flow Management: Configurable. Possibility to change test/voltage in just one wafer touch.
- Consumable Parts: Full flexibility of Prober and Tester. Probe Cards are only for connection.
- Automation: Fully guaranteed. No needs to manually move Wafer or Probe Card + SECSGEM compliancy.
- Test during Probing capability: Indexing feature for higher gross size
- Burn-in time overhead: No additional time on top of the BI time. Chuck is already at high temperature and automatic loading is negligible.
- Typical test time: 40min/3h
- Throughput: 32 wafer/day in a single stage. 160 in the 5 stages version.
Equipment Software Platform
The system’s Software Test Environment provides the complete set of tools for Test development (SW Development package), Production execution and Reporting (SW Execution package).
With its rich set of graphical user interface, the SocrATE/AWL-BITS software offers the engineering tools necessary to characterize devices, as well as develop and debug test programs quickly and efficiently.
Pattern Editor
- New IDE for pattern viewer and editor based on EDA platform vectors
- Easy Test program generation
Test Plan Editor
- Features for easier engineering activities
- Easier operator interface
Data Viewer
- Powerful data reporting and analysis, which includes dedicated Burn-in data format, STDF output and STIF Map Management
- Run-time access to test-flow steps, parameters and measures
- Detailed report on the analyzed data
Contact us
In addition to the significant existing products’ portfolio, EDA Industries is specialized in meeting specific customer requests by customizing its solutions or by designing new ones.
For further info, please send a direct request to sales@eda-industries.com