Wafer Level Burn-in

By interpreting SiC and GaN mega-trend, EDA designed SocrATE project, putting in place all the skills to develop an exclusive product, in line with the expectations of the AUTOMOTIVE market such as Testing Coverage, Quality and lowest Test cost.

 

System features

SocrATE is a complete Burn-in test system designed specifically to meet the needs of cost-sensitive volume manufacturing of current and next generation SiC, GaN and High Voltage devices.

SocrATE offers true site-independent test across a broad range of software-controlled configurations. The innovative architecture backs each of the system's 1800 or 3600 sites with a fully independent Test system.

 

Prober

The proposed Prober technology with common Loader and Unloader solution is composed by:

5cell MS-WLBI system with:

- 1 common loader/unloader for the complete System

- Probe card clamping system up to 520mm

- Cassette docking port (FOUP) for 6" and 8"

- ZERO Footprint Manipulator

- 6" and 8" Bernoulli handling system

- Room temperature to hot control (Room temp ~ 250'C)

- N2 supply solution for chamber

- 6" & 8" Wafer size chuck for 6" SiC wafer and 8" TAIKO wafer (Gold plating, Multi hole, w/o 3pin riser)

- SECSGEM Automation

 

Tester

EDA philosophy has always been oriented towards the needs of Customer using cutting edge solutions to produce practical and easy to use products which are constantly upgraded over time.

In particular for this purpose we can offer a range of 2 Tester configurations specially created for the MS-WLBI Equipment.

$11-    Basic Tester for Burn-in stress on 1800Dice, called AWL-BITS 1800.

$12-    Upgrade for Burn-in stress on additional 1800 Dice for a total of 3.600 Dice in parallel, called AWL-BITS 3600.

EDA Tester proposal has a modular true site-independent test architecture based on a BASIC electronic configuration to perform a typical Burn-in stress on 1800Dice in parallel.

This Basic platform can be upgraded over time to increase the Burn-in capacity up to 3.600 Dice in parallel.

Every Cell has its own Tester to perform an independent Test Flow including stress sequence up to 2500V and parametric test sequence (Vth, BVDss, IDSX and IGSS).

 

Software

The system's enhanced SW Test Environment provides the complete set of software tools for Test development (SW Development package), Production execution and Reporting (SW Execution package).

To speed devices to market quickly, the AWL-BITS software provides the engineering tools necessary to characterize devices as well as develop and debug test programs quickly and efficiently.

AWL-BITS rich set of interactive, graphical user interface(GUI) based development, debug and production.

 

Dimension and Workcell Area

The combination of high performance architecture and compact design enables the AWL-BITS to provide the industry's highest unit volume per square foot well beyond any other system.

The system provides twice parallelism in half the Workcell area than any standard Test Cell.

 

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